Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

A developer has successfully ported the Project Oberon operating system to run on RISC-V hardware, replacing the original RISC-5 architecture. This achievement was shared in a Show HN post and marks a significant step in demonstrating Oberon’s portability to modern open-source hardware platforms. The developer emphasized that this port is still in early testing stages but shows promising compatibility.

The project involves adapting the Oberon system, originally designed for the RISC-5 architecture used in the original Oberon hardware, to run on RISC-V, an open-source instruction set architecture gaining popularity in academia and industry. The developer, whose identity has not been publicly disclosed, shared the port in a Show HN post, claiming it functions on RISC-V hardware with basic system operations confirmed.

According to the developer, the port includes core components of the Oberon OS, such as the file system, user interface, and basic I/O, though some features remain under development. The port was tested on a RISC-V development board, with initial results indicating successful booting and operation of essential system functions. The developer noted that performance and full hardware support are still being optimized.

Potential Impact of Oberon on Modern Hardware Development

This port demonstrates that the Oberon system can be adapted to modern open-source architectures like RISC-V, potentially broadening its use in educational, experimental, and embedded systems. It highlights the flexibility of Oberon’s design, which was originally created in the 1980s, and suggests that legacy systems can be modernized for current hardware platforms. The development could inspire further porting efforts, fostering a renewed interest in Oberon’s simplicity and efficiency for contemporary use cases.

Historical and Technical Background of Oberon and RISC-V

Project Oberon was developed by Niklaus Wirth and colleagues at ETH Zurich in the 1980s as both a programming language and an operating system designed for simplicity and efficiency. Originally running on custom hardware with the RISC-5 architecture, Oberon has been influential in computer science education and research. RISC-V, an open-source instruction set architecture, emerged in the 2010s as a flexible, royalty-free alternative to proprietary architectures, gaining traction in academia and industry for its modularity and openness. Prior to this port, Oberon was largely confined to its original hardware and emulators, with limited efforts to adapt it to modern architectures.

The recent port, as shared in the Show HN post, marks a notable step in bridging the gap between legacy OS design and modern hardware platforms. While RISC-V has been used in various experimental OS projects, running Oberon on RISC-V had not been publicly demonstrated before this effort.

“This port proves that Oberon can run on modern open-source hardware, opening new possibilities for education and experimentation.”

— the developer

Extent of Compatibility and Future Development Stages

It is not yet clear how fully functional the RISC-V port is across different hardware configurations or how extensive the feature set will become in subsequent updates. The developer has indicated ongoing work to improve hardware support and performance, but details about compatibility with various RISC-V boards or peripherals remain undisclosed. Additionally, it is uncertain whether this port will lead to broader community adoption or remain a personal project.

Next Steps for Testing and Community Engagement

The developer plans to continue testing the RISC-V port on different hardware platforms and aims to improve system stability and hardware support. They also intend to share detailed documentation and source code to encourage community involvement. Further updates could include performance benchmarks, expanded feature support, and possibly a public release for wider testing. The project’s progress will likely influence future efforts to modernize legacy OS systems like Oberon for open hardware architectures.

Key Questions

What hardware is required to run Oberon on RISC-V?

Currently, the port was tested on a specific RISC-V development board. Details about the exact hardware specifications have not been fully disclosed, but it involves standard RISC-V cores compatible with the port’s implementation.

Is the port fully functional or still experimental?

The port is in early testing stages, with basic system functions confirmed. Many features are still under development, and full hardware and peripheral support are not yet available.

Will the source code be available for public use?

The developer has indicated plans to share the code and documentation to foster community involvement, but a public release date has not been specified.

How does this development impact the future of Oberon?

This port demonstrates Oberon’s adaptability to modern hardware, potentially inspiring further development, educational use, and experimental projects on open-source architectures like RISC-V.

Could this lead to new applications for Oberon?

Yes, if further optimized, Oberon could find applications in embedded systems, educational platforms, or experimental hardware projects leveraging RISC-V’s openness.

Source: hn